Please use this identifier to cite or link to this item:https://hdl.handle.net/20.500.12259/56551
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dc.contributor.authorMan, Ka Lok-
dc.contributor.authorLei, Chi-Un-
dc.contributor.authorKapoor, Hemangee K-
dc.contributor.authorKrilavičius, Tomas-
dc.contributor.authorMa, Jieming-
dc.contributor.authorZhang, Nan-
dc.coverage.spatialSK-
dc.date.accessioned2018-10-07T00:56:59Z-
dc.date.available2018-10-07T00:56:59Z-
dc.date.issued2016-
dc.identifier.issn13359150-
dc.identifier.otherVDU02-000019847-
dc.identifier.urihttp://cai.type.sk/content/2016/1/pafsv-a-formal-framework-for-specification-and-analysis-of-systemverilog/-
dc.description.abstractWe develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800TM SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800TM SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800TM SystemVerilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiteren
dc.description.sponsorshipBaltijos pažangių technologijų institutas, Vilnius-
dc.description.sponsorshipInformatikos fakultetas-
dc.description.sponsorshipTaikomosios informatikos katedra-
dc.description.sponsorshipVytauto Didžiojo universitetas-
dc.format.extentp. 143-176-
dc.language.isoen-
dc.relation.ispartofComputing and informatics. Bratislava : Slovak Academy of Sciences, Institute of Informatics, 2016, Vol. 35, iss. 1-
dc.relation.isreferencedbyScience Citation Index Expanded (Web of Science)-
dc.relation.isreferencedbyApplied Science & Technology Source (EBSCO)-
dc.relation.isreferencedbyComputers & Applied Sciences Complete (EBSCO)-
dc.subjectPAFSVlt
dc.subjectVeriloglt
dc.subjectProcesų algebroslt
dc.subjectFormali semantikalt
dc.subjectGrandinių verifikavimaslt
dc.subjectPAFSVen
dc.subjectSystemVerilogen
dc.subjectProcess algebrasen
dc.subjectFormal semanticsen
dc.subjectCircuit verificationen
dc.subject.otherInformatika / Informatics (N009)-
dc.subject.otherInformatikos inžinerija / Informatics engineering (T007)-
dc.titlePAFSV: a formal framework for specification and analysis of SystemVerilogen
dc.typeStraipsnis Clarivate Analytics Web of Science ar/ir Scopus / Article in Clarivate Analytics Web of Science or / and Scopus (S1)-
dc.identifier.isiWOS:000375970000007-
dcterms.bibliographicCitation48-
dc.date.updated2020-01-30T16:22Z-
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crisitem.author.deptFizikos katedra-
crisitem.author.deptFizikos katedra-
crisitem.author.deptFizikos katedra-
crisitem.author.deptTaikomosios informatikos katedra-
crisitem.author.deptFizikos katedra-
crisitem.author.deptFizikos katedra-
Appears in Collections:Universiteto mokslo publikacijos / University Research Publications
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